The Bus Matrix manages five Masters and five Slaves.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master.
Each Slave has its own arbiter, thus allowing a different arbitration per Slave.
According to upper, The Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each AHB Master several memory mappings. Depending on the product, each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e.,external RAM, internal ROM, internal Flash, etc.) becomes possible.
For Master 0 and Master 1 (ARM926™ Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap. Refer to Table 8-3 for details.
For Master 0 and Master 1 (ARM926™ Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap. Refer to Table 8-3 for details.
Boot Strategiesalmost all systems boots at address 0x0. To ensure a maximum number of possibilities for boot,the memory layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted for each Master of the Bus Matrix.
When REMAP = 1, BMS is ignored. Refer to the Bus Matrix Section for more details.
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an
external memory.
This is done via hardware at reset.
Note: Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in Figure 8-1 on page 16.
The AT91SAM9261S Bus Matrix manages a boot memory that depends on the level on the
BMS pin at reset.
The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
BMS = 1, Boot on Embedded ROM
The system boots using the Boot Program.
• DataFlash Boot
– Downloads and runs an application from SPI DataFlash into internal SRAM
– Downloaded code size from SPI DataFlash depends on embedded SRAM size
– Automatic detection of valid application
– SPI DataFlash connected to SPI NPCS0
• NANDFlash Boot
• Boot Uploader in case no valid program is detected in external SPI DataFlash
– Small monitor functionalities (read/write/run) interface with SAM-BA™ application
– Automatic detection of the communication link
Serial communication on a DBGU (XModem protocol)
USB Device Port (CDC Protocol)
BMS = 0, Boot on External Memory
• Boot on slow clock (32,768 Hz)
• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit
data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take
the following steps:
1. Program the PMC (main oscillator enable or bypass mode).
2. Program and start the PLL.
3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them
to the new clock
4. Switch the main clock to the new value.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted for each Master of the Bus Matrix.
When REMAP = 1, BMS is ignored. Refer to the Bus Matrix Section for more details.
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an
external memory.
This is done via hardware at reset.
Note: Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in Figure 8-1 on page 16.
The AT91SAM9261S Bus Matrix manages a boot memory that depends on the level on the
BMS pin at reset.
The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
BMS = 1, Boot on Embedded ROM
The system boots using the Boot Program.
• DataFlash Boot
– Downloads and runs an application from SPI DataFlash into internal SRAM
– Downloaded code size from SPI DataFlash depends on embedded SRAM size
– Automatic detection of valid application
– SPI DataFlash connected to SPI NPCS0
• NANDFlash Boot
• Boot Uploader in case no valid program is detected in external SPI DataFlash
– Small monitor functionalities (read/write/run) interface with SAM-BA™ application
– Automatic detection of the communication link
Serial communication on a DBGU (XModem protocol)
USB Device Port (CDC Protocol)
BMS = 0, Boot on External Memory
• Boot on slow clock (32,768 Hz)
• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit
data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take
the following steps:
1. Program the PMC (main oscillator enable or bypass mode).
2. Program and start the PLL.
3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them
to the new clock
4. Switch the main clock to the new value.
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